1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a high speed DRAM (Dynamic Random Access Memory) used for an embedded DRAM and the like. In particular, the invention relates to a row-related control circuit of the high speed DRAM.
2. Description of the Background Art
FIG. 25 is a schematic diagram illustrating an arrangement of row-related circuitry of a conventional DRAM. DRAM shown in FIG. 25 is a clock synchronous DRAM (SDRAM) having a 4-bank structure and storage capacity of 64 Mbits.
Referring to FIG. 25, the DRAM includes four memory mats MMA-MMD allocated respectively to banks A-D. Memory mats MMA-MMD each have the storage capacity of 16 Mbits. Memory mats MMA-MMD are each divided into 16 memory sub blocks MSB each having the storage capacity of 1 M bit. In each of memory mats MMA-MMD, a sense amplifier band SAB including a sense amplifier circuit for sensing, amplifying and latching data in a memory cell of a selected row is arranged between memory sub blocks MSB adjacent to each other.
Row-related control circuits CTA-CTD are respectively associated with memory mats MMA-MMD, and row-related control circuits CTA-CTD each receive externally supplied clock signal extCLK, row address signal RA less than 11:0 greater than , bank address signal BA less than 1:0 greater than and a command (not shown) to generate a row-related control signal. Row-related control circuits CTA-CTD generate, when designated by bank address signal BA less than 1:0 greater than , row predecode signals X_A less than 19:0 greater than -X_D less than 19:0 greater than  and block selection signals BS_A less than 7:0 greater than -BS_D less than 7:0 greater than  according to row address signal RA less than 11:0 greater than  applied in synchronization with external clock signal extCLK. 8-bit block selection signal allows two memory sub blocks MSB in a bank (memory mat) designated by bank address signal BA less than 1:0 greater than  to be selected.
When a row-related command (bank activation command; active command) is supplied, row-related control circuits CTA-CTD are selectively activated according to bank address signal BA less than 1:0 greater than  so as to generate row address enable signals RADE_A-RADE_D and word line activation signals RXT_A-RXT_D in synchronization with external clock signal extCLK.
Row-related control circuits CTA-CTD are arranged corresponding to respective memory mats MMA-MMD and these row-related control circuits CTA-CTD are selectively driven according to bank address signal BA less than 1:0 greater than , so that banks A-D can be driven independently into an active state.
For each memory sub block MSB of memory mats MMA-MMD, there are provided a spare determination circuit (fuse box) 4 for determining whether or not a defective row is addressed, and a row decode circuit 5 for driving memory cells of one row in an associated memory sub block into a selected state according to a corresponding block selection signal among block selection signals BS_A less than 7:0 greater than -BS_D less than 7:0 greater than  and a corresponding predecode signal among row predecode signals X_A less than 19:0 greater than -X_D less than 19:0 greater than . In each of memory mats MMA-MMD, word line selection is performed in each memory sub block MSB and repair of a defective row is done by a redundant row (row spare circuit) in each memory sub block MSB. High-order signal RA less than 11:9 greater than of the row address is decoded so as to generate block selection signals BS_A less than 7:0 greater than -BS_D less than 7:0 greater than  when respective row-related control circuits CTA-CTD are activated. Row predecode signals X_A less than 19:0 greater than -X_D less than 19:0 greater than  are generated from row address signal RA less than 8:0 greater than .
FIG. 26A illustrates a structure of a row-related control signal generation circuit of the row-related control circuit. FIG. 26A representatively shows one row-related control circuit CT since row-related control circuits CTA-CTD have the same structure.
Referring to FIG. 26A, row-related control circuit CT includes a composite gate circuit 900 receiving active command ACT instructing bank activation and precharge command PRG instructing bank inactivation, a latch circuit 901 for latching an output signal of composite gate circuit 900 in synchronization with rising of internal clock signal CLK, a delay circuit 902 for delaying, by predetermined time D1, bank activation signal RASE received from latch circuit 901, an AND circuit 903 receiving an output signal of delay circuit 902 and bank activation signal RASE, a delay circuit 904 for delaying, by predetermined time D2, an output signal of AND circuit 903, and an OR circuit 905 receiving an output signal of delay circuit 904 and an output signal of AND circuit 903 to generate row address enable signal RADE. Delay circuit 902 and AND circuit 903 constitute a rise delay circuit while delay circuit 904 and OR circuit 905 constitute a fall delay circuit.
Row-related control circuit CT further includes a delay circuit 906 for delaying bank activation signal RASE by predetermined time D3, an AND circuit 907 receiving an output signal of delay circuit 906 and bank activation signal RASE, a delay circuit 908 for delaying an output signal of AND circuit 907 by predetermined time D4, and an OR circuit 909 receiving an output signal of delay circuit 908 and an output signal of AND circuit 907 to generate word line activation signal RXT.
Composite gate circuit 900 is equivalent to a circuit that includes an OR circuit receiving bank activation signal RASE and active command ACT and a gate circuit receiving an output signal of the OR circuit and precharge command PRG. The gate circuit operates as a buffer circuit when precharge command PRG is in an inactive state of L (logic low) level. Internal clock signal CLK generated from external clock signal extCLK is a clock signal synchronized with external clock signal extCLK. Now, an operation of row-related control circuit CT shown in FIG. 26A is described in conjunction with the timing chart shown in FIG. 26B.
In cycle #0 of clock signal CLK, active command ACT is supplied and an output signal of composite gate circuit 900 rises to H (logic high) level. The output signal of composite gate circuit 900 is latched by latch circuit 901 synchronously with rising of internal clock signal CLK, and bank activation signal RASE rises to an active state of H level. After bank activation signal RASE rises to H level, an output signal of AND circuit 903 rises to H level after delay time D1 of delay circuit 902 has passed, and accordingly row address enable signal RADE rises to H level.
In response to rising of bank activation signal RASE, an output signal of AND circuit 907 rises to H level after delay time D3 of delay circuit 906 has passed, and accordingly word line activation signal RXT rises to H level.
Although active command ACT falls to L level, latch circuit 901 is brought into latched state in synchronization with rising of internal clock signal CLK so that bank activation signal RASE is maintained in the active state of H level.
In clock cycle #1, when active command ACT is not supplied (when active command ACT is at L level), bank activation signal RASE is at H level and accordingly an output signal of composite gate 900 is at H level so that latch circuit 901 takes in and latches a signal of H level from composite gate 900. In this way, bank activation signal RASE is maintained in the active state of H level until precharge command PRG is supplied (precharge command PRG attains H level), and accordingly row address enable signal RADE and word line activation signal RXT each are maintained in the active state of H level.
In clock cycles #1-#4, a column-related operation is performed (a read command instructing a data reading or a write command instructing a data writing is supplied).
In clock cycle #5, when precharge command PRG is supplied, an output signal of composite gate 900 falls to L level, latch circuit 901 takes in a signal of L level from composite gate circuit 900 at the rising edge of internal clock signal CLK, and accordingly bank activation signal RASE reaches the inactive state of L level. When bank activation signal RASE falls to L level and accordingly an output signal of AND circuit 903 falls to L level, row address enable signal RADE reaches the inactive state of L level after delay time D2 of delay circuit 902 has passed. Further, after delay time D4 of delay circuit 904, word line activation signal RXT reaches the inactive state of L level. Delay time D2 is longer than delay time D4, so that after word line activation signal RXT and a word line (main/sub word line) in the selected state each reach the inactive state, row address enable signal RADE enters the inactive state and the latched state of the row address signal is released as described later.
FIG. 27 illustrates a structure of an internal address generation circuit included in row-related control circuit CT. A row address signal has a plurality of bits and address generation circuits of the same structure are provided for respective bits. FIG. 27 representatively illustrates one row address generation circuit.
Referring to FIG. 27, the row address generation circuit includes a latch circuit 910 latching row address signal RA synchronously with rising of internal clock signal CLK, an inverter 911 inverting row address enable signal RADE, a transmission gate 912 allowing output signal XA of latch circuit 910 to pass according to an output signal of inverter 911 and row address enable signal RADE, an inverter 913 inverting address signal XA supplied via transmission gate 912, an inverter 914 inverting an output signal of inverter 913 for transmission to an input of inverter 913, an AND circuit 915 receiving address signal XA and row address enable signal RADE supplied via transmission gate 912 to generate internal row address signal RAD, and an AND circuit 916 receiving row address enable signal RADE and an output signal of inverter 913 to generate internal row address signal ZRAD.
Inverters 913 and 914 constitute an inverter latch. Transmission gate 912 enters a nonconductive state when row address enable signal RADE is in the active state of H level. An operation of the row address generation circuit shown in FIG. 27 is described in conjunction with the timing chart shown in FIG. 28.
When active command ACT is supplied, latch circuit 910 latches address signal RA synchronously with rising of internal clock signal CLK and outputs latched row address signal XA. Row address enable signal RADE is in the inactive state of L level and transmission gate 912 is in a conductive state to allow latched row address signal XA from latch circuit 910 to pass.
When row address enable signal RADE is driven into the active state of H level according to the active command, transmission gate 912 enters the nonconductive state, and latched row address signal XA from latch circuit 910 is latched by inverters 913 and 914. Subsequently, even if row address signal XA output from latch circuit 910 varies during the active state of row address enable signal RADE, the internal row address signal is not influenced at all, because transmission gate 912 is nonconductive.
AND circuits 915 and 916 maintain internal row address signals RAD and ZRAD in the inactive state of L level when row address enable signal RADE is at L level. Then, when row address enable signal RADE is driven into the active state, AND circuits 915 and 916 drive row address signals RAD and ZRAD into a corresponding logic state according to the address signal latched by inverters 913 and 914.
Internal row address signals ZRAD and RAD are address signals complementary to each other and their logic levels are held during the period of the active state of H level of row address enable signal RADE. During the active state of H level of row address enable signal RADE, internal row address signals RAD and ZRAD have respective logic levels held. In a similar manner, according to word line activation signal RXT, a word line corresponding to an addressed row can be driven into the selected state so that the selected word line is maintained in the selected state during the period in which the bank is activated.
FIG. 29A is a schematic diagram illustrating a portion for generating a block selection signal included in row-related control circuit CT. Referring to FIG. 29A, the block selection signal generation portion includes a block decode circuit 920 for decoding internal row address signals RAD less than 11:9 greater than  and ZRAD less than 11:9 greater than  to generate block selection signal BS less than 7:0 greater than . Block decode circuit 920 includes a block decoder provided for each of block selection signals BS less than 7 greater than -BS less than 0 greater than . The block decoder is a 3-bit decoder.
FIG. 29B illustrates one example of the block decoder included in block decode circuit 920. Referring to FIG. 29B, a block decoder 920a receives 3-bit internal row address signal bits RAD less than 11 greater than , RAD less than 10 greater than  and RAD less than 9 greater than  to generate block selection signal BS less than 7 greater than . 8-bit block selection signal BS less than 7:0 greater than  allows two of sixteen memory sub blocks to be selected. Appropriately combined high-order 3 bits of the row address signal are supplied to block decoder 920a so as to selectively activate block selection signals BS less than 7 greater than -BS less than 0 greater than .
FIG. 30 is a schematic diagram illustrating a structure of a row predecode circuit included in row-related control circuit CT. Referring to FIG. 30, row predecode circuit 930 includes a predecode circuit 930a receiving and predecoding internal row address signals RAD less than 1:0 greater than  and ZRAD less than 1:0 greater than  to generate 4-bit predecode signal X less than 3:0 greater than , a predecode circuit 930b receiving and predecoding internal row address signals RAD less than 3:2 greater than  and ZRAD less than 3:2 greater than  to generate 4-bit predecode signal X less than 7:4 greater than , a predecode circuit 930c receiving and predecoding internal row address signals RAD less than 6:4 greater than  and ZRAD less than 6:4 greater than  to generate 8-bit predecode signal X less than 15:8 greater than , and a predecode circuit 930d receiving and predecoding internal row address signals RAD less than 8:7 greater than  and ZRAD less than 8:7 greater than  to generate 4-bit predecode signal X less than 19:16 greater than .
Each of predecode circuits 930a-930d includes a predecode circuit similar to the decode circuit shown in FIG. 29B as a unit predecode circuit. Predecode signal X less than 19:0 greater than  from row predecode circuit 930 designates memory cells of one row in a memory sub block having memory cells of 512 rows. For example, predecode signal X less than 19:16 greater than  designates a group of memory cells of 128 rows among the memory cells of 512 rows. Predecode signal X less than 15:8 greater than  designates a group of memory cells of 16 rows among a group of memory cells of 128 rows. Predecode signal X less than 7:4 greater than  designates a group of memory cells of 4 rows among a group of memory cells of 16 rows. Predecode signal X less than 3:0 greater than  designates memory cells of one row among a group of memory cells of 4 rows.
Predecode signal X less than 19:0 greater than  is supplied to a corresponding memory mat (bank) together with block selection signal BS less than 7:0 greater than , and a row decode circuit provided in each memory sub block is activated according to the block selection signal. Then, a row decoding operation is carried out and the memory cells of one row designated by predecode signal X less than 19:0 greater than  in a memory sub block designated by block selection signal BS less than 7:0 greater than  is driven into the selected state.
FIG. 31 is a schematic diagram illustrating spare determination circuit 4 provided for each memory sub block. Referring to FIG. 31, spare determination circuit 4 includes: a precharging P channel MOS transistor PT which is turned on when bank activation signal RASE is inactivated to precharge an output signal line SG to supply voltage Vcc level, fuse elements F4-F19 connected in parallel to output signal line SG; and N channel MOS transistors RT4-RT19 which are connected in series to fuse elements F4-F19 respectively and receive, at respective gates, predecode signals X less than 4 greater than -X less than 19 greater than . The sources of MOS transistors RT4-RT19 are connected to the ground node. Spare determination result instruction signal SPARE_E is output from output signal line SG.
One of fuse elements F7-F4 corresponding to predecode signal X less than 7:4 greater than  is blown and one of fuse elements F15-F8 corresponding to predecode signal X less than 15:8 greater than  is cut, and one of fuse elements F19-F16 corresponding to predecode signal X less than 19:16 greater than  is cut so that a defective row address is programmed.
In a normal operation, when bank activation signal RASE is in the inactive state, MOS transistor PT is conductive and output signal line SG is at H level. When bank activation signal RASE attains the active state of H level, MOS transistor PT is turned off and the precharging operation of output signal line SG is completed. Then, predecode signal X less than 19:4 greater than  is supplied. Among fuse elements F4-F19, a fuse element corresponding to a predecode signal that attains H level when a defective row address is designated is blown. When a defective row address is designated by predecode signal X less than 19:4 greater than , there is no path through which current flows from output signal line SG to the ground node, and spare determination result instruction signal SPARE_E is maintained at H level. On the other hand, if predecode signal X less than 19:4 greater than  is different from the defective row address, at least one of MOS transistors connected in series to a conductive fuse element is turned on, output signal line SG is coupled to the ground node, and accordingly spare determination result instruction signal SPARE_E is driven into L level. Accordingly, determination is made on whether or not a defective row address is designated.
Predecode signal X less than 3:0 greater than  is not used in spare determination circuit 4 for the reason below. In the memory array, the word lines have a hierarchical word line structure including main word lines and sub word lines. Memory cells of one row are connected to a sub word line and one main word line is allocated to a set of a predetermined number of sub word lines. If one main word line is allocated to four sub word lines, one of four sub word lines is designated by predecode signal X less than 3:0 greater than . In this way, the spare circuit repairs any defect for each main word line so that four sub word lines are replaced simultaneously.
FIG. 32 is a schematic diagram illustrating a structure of a row decode circuit provided for a memory sub block. Referring to FIG. 32, in memory sub block MSB, a normal main word line NMWL, four normal sub word lines NSWL0-NSWL3 corresponding to normal main word line NMWL, and sub word drivers SWD0-SWD3 corresponding to respective normal sub word lines NSWL0-NSWL3 for driving respective sub word lines into the selected state according to sub decode signals SD0-SD3 and a signal on normal main word line NMWL are provided. As a spare circuit, a spare main word line SMWL, four spare sub word lines SSWL0-SSWL3 corresponding to spare main word line SMWL, and spare sub word line drivers SSD0-SSD3 corresponding to respective spare sub word lines SSWL0-SSWL3 for driving respective sub word lines into the selected state according to sub decode signals SD0-SD3 and a signal on spare main word line SMWL are provided. Memory cells in memory sub blocks MSB are connected to sub word lines NSWL0-NSWL3 and SSWL0-SSWL3, respectively.
Spare determination result instruction signal SPARE_E from spare determination circuit 4 is supplied to a spare enable circuit 4a and accordingly normal row enable signal NRE and spare row enable signal SRE are generated. A row decoder 5a associated with normal main word line NMWL is enabled, when normal row enable signal NRE and block selection signal BS are activated, to decode predecode signals Xi, Xj and Xk for driving normal main word line NMWL into the active state according to the result of the decoding and word line activation signal RXT. Predecode signals Xi, Xj and Xk correspond to predecode signals X less than 7:4 greater than , X less than 15:8 greater than  and X less than 19:16 greater than , respectively. Sub decode signals SD0-SD3 are generated from predecode signal X less than 3:0 greater than  (in the form of a pair of complementary signals), respectively.
A spare word line driver 5b associated with spare main word line SMWL is enabled, when spare row enable signal SRE from spare enable circuit 4a and block selection signal BS are activated, to drive spare main word line SMWL to the selected state according to word line activation signal RXT. Spare determination circuit 4 is provided for spare main word line SMWL. Therefore, when spare determination result instruction signal SPARE_E of one spare determination circuit attains L level, spare row enable signal SRE is activated and spare main word line SMWL is driven into the selected state. At this time, normal row enable signal NRE is in the inactive state so that row decoder 5a is prevented from decoding and driving main word line NMWL into the selected state.
Only in memory sub block MSB selected by block selection signal BS, a word line (main and sub word lines) is driven into the selected state.
FIG. 33 is a timing chart illustrating a row selecting operation in one bank. In cycle #a of internal clock signal CLK, active command ACT is supplied. In clock cycle #a, bank activation signal RASE is activated according to active command ACT at the rising edge of internal clock signal CLK (see FIG. 26A).
Following the activation of bank activation signal RASE, row address enable signal RADE is activated. In response to the activation of row address enable signal RADE, externally supplied address signal RA is latched as shown in FIG. 27 and internal row address signal RAD less than 8:0 greater than  is defined. Internal row address signals RAD less than 8:0 greater than  and ZRAD less than 8:0 greater than  are predecoded to generate predecode signal X less than 19:0 greater than  and block selection signal BS less than 7:0 greater than . Block selection signal BS less than 7:0 greater than  and row predecode signal X less than 19:0 greater than  are transmitted from row-related control circuit CT located at the central portion to a corresponding memory mat. In each memory sub block, spare determination and decoding of a predecode signal are carried out.
In the spare determination, spare determination result instruction signal SPARE_E is defined after predecode signal X less than 19:4 greater than  is defined, and normal row enable signal NRE and spare row enable signal SRE are generated according to spare determination result instruction signal SPARE_E (see FIG. 32). After the spare determination result is defined, a row decoder or a spare word line driver is enabled and an associated word line (main word line) is driven into the selected state according to word line activation signal RXT.
Specifically, when a main word line is driven into the selected state after active command ACT is supplied, an addressed main word line is driven into the selected state by a row decoder or a spare word line driver after time ta for address predecode, propagation time of the predecode signal and spare determination time tb are passed, and then a sub word line (normal sub word line or spare sub word line) is driven into the selected state. In other words, the actual time required for driving a word line (sub word line) into the selected state after active command ACT is supplied is time td (ta+tb less than td). In clock cycle #a, after active command ACT is supplied, a command (read or write command READ or WRITE) for operating the column-related circuitry is supplied.
Time tRCD required from start of operation of the row-related circuitry to the start of operation of the column-related circuitry is known as RAS-CAS delay time in a standard DRAM. If time (row access time) td from supply of active command ACT to driving of the sub word line to the selected state is long, RAS-CAS delay time tRCD cannot be shortened. Consequently, when internal operation is to be synchronized with high speed internal clock signal CLK, the read command or write command cannot be supplied immediately after active command ACT is supplied. Therefore, even if high speed internal clock signal CLK is employed, a high speed data access cannot be implemented.
Further, as shown in FIG. 31, the spare determination circuit uses predecode signal X less than 19:4 greater than  so that fuse elements F19-F4 should be arranged respectively for bits X less than 19 greater than -X less than 4 greater than  of the predecode signal, because the predecode signal is transmitted from the row-related control circuit in parallel with a block selection signal. Fuse elements F19-F4 are significantly large in size compared with a normal MOS transistor. The fuse elements occupy the large area since they are cut by a process such as laser blowing. In addition, the spaces between fuse elements F19-F4 are sufficiently large so as to prevent an adverse influence caused by scattering of the fractions of the fuse elements which are generated in the laser blowing. Since there are a large number of fuse elements such as F19-F4, the occupying area of the spare determination circuit is accordingly large and thus the chip area increases.
As shown in FIG. 25, memory mats MMA-MMD are allocated to banks A-D respectively and row-related control circuits CTA-CTD are arranged corresponding to banks A-D respectively. In recent years, at least four banks are required in a high speed memory such as the logic-merged DRAM and Rambus DRAM (RDRAM). When a large number of banks are required, it is difficult to allocate a memory mat to one bank because of a resultant significant increase of the chip area.
Further, in the structure having a row-related control circuit for each bank and predecode signal lines dedicated to that bank, increase of the number of banks increases the area of row-related control circuits and predecode signal line region and thus increases the chip area.
An object of the present invention is to provide a semiconductor memory device capable of shortening a row access time required for word line activation and easily adaptable to bank expansion.
Another object of the present invention is to provide a semiconductor memory device adaptable to bank expansion without increase of the area and increase of the row access time.
A further object of the invention is to provide a semiconductor memory device having an improved row-related circuit that can overcome those disadvantages of the conventional DRAM.
According to one aspect of the invention, a semiconductor memory device includes a memory array having a plurality of banks, a central control circuit arranged on one side of the memory array and receiving externally supplied clock signal and address signal for generating an internal clock signal and an internal address signal asynchronous with the internal clock signal to transmit the generated signals in common to the banks of the memory array in one direction, a preprocessing circuit provided for each of a plurality of banks of the memory array and latching and predecoding the internal address signal synchronously with a latch timing signal to generate a predecode signal, and a selection circuit provided for each of a plurality of banks of the memory array for selecting an addressed memory cell of the corresponding bank according to the predecode signal from a corresponding preprocessing circuit.
According to a second aspect of the invention, a semiconductor memory device includes a memory array divided into a plurality of banks that are driven into active state independently of each other, each bank divided into a plurality of sub blocks each having a plurality of memory cells. A plurality of banks each include a predetermined number of sub blocks.
According to the second aspect of the invention, the semiconductor memory device further includes a control signal generation circuit shared by a plurality of banks for supplying, to each bank, a control signal for driving a designated bank into active state according to a bank activation instruction signal, a block selection signal generation circuit shared by a plurality of banks for latching a block selection signal supplied in parallel with the bank activation instruction signal synchronously with an externally supplied clock signal and supplying the block selection signal commonly to a plurality of banks, an address generation circuit supplying an address signal externally supplied asynchronously with the clock signal commonly to a plurality of banks, and a preprocessing circuit provided for each of a plurality of banks for latching the address signal from the address generation circuit according to a latch timing signal and decoding the latched address signal when an operation control signal included in the control signal is activated. The operation control signal is set in the active state during the period in which a corresponding bank is set in the active state by the bank activation instruction signal.
According to the second aspect of the invention, the semiconductor memory device further includes a spare determination circuit provided for each of a plurality of banks, for determining whether or not the address signal from the address generation circuit designates a defective bit address based on the address signal and a programmed defective bit address to output a spare determination result instruction signal indicating the result of the determination, a spare latch circuit latching an output signal of the spare determination circuit according to a latch timing signal, and a spare enable circuit generating a spare enable signal for activating a spare circuit for repairing a defective bit according to an output signal of the spare latch circuit.
An address signal is commonly applied from the central control circuit to a plurality of banks asynchronously with an internal clock signal, and then predecoded in each bank synchronously with a latch timing signal. Accordingly, the address signal can be transmitted to each bank utilizing the address set up time and thus the time required for propagation of the address signal can be shortened. In addition, the address signal is transmitted commonly to a plurality of banks in one direction. Even if the number of banks included in the memory array increases, there is no increase in the number of transmitted address signals and bits so that the semiconductor memory device is easily adaptable to bank expansion.
The spare determination operation is done utilizing the address signal and the spare determination result signal is latched according to the latch timing signal so as to perform a subsequent predecode operation. In this way, the spare determination can be done utilizing the address set up time so as to decrease the time required for address propagation and spare determination. Consequently, the row access time can be reduced. Since the address signal is commonly transmitted to a plurality of banks, the semiconductor memory device is easily adaptable to bank expansion.
The control signal is transmitted to each respective bank. Therefore, even if the address signal is commonly transmitted to a plurality of banks, a designated operation is correctly performed only in a designated bank.
As heretofore described, a semiconductor memory device capable of accomplishing high speed access without increase of the chip area even if bank expansion is done can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.